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Dual-Core Delfino Microcontroller » TMS320F28377D

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Dual-Core Delfino Microcontroller - TMS320F28377D

The TMS320F2837xD device introduces the TMU, which is an accelerator that greatly reduces the number of cycles required to perform common trigonometric functions. The TMS320F2837xD device also has a second-generation Viterbi Complex Math Unit, VCU-II, with improved acceleration on Viterbi operations, complex multiplies, and the CRC engine.

The TMS320F2837xD device supports up to 1MB of ECC-protected on-board flash memory and up to 204KB of SRAM with either ECC or parity. Two independent security zones are also available for 128-bit code protection. High-precision control peripherals such as enhanced pulse width modulators (ePWMs) with fault protection, encoders, and captures are also included.

Features:

  • Dual-Core Architecture
    • Two TMS320C28x 32-Bit CPUs
    • 200 MHz (5-ns Cycle Time)
    • IEEE 754 Single-Precision Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
    • Viterbi/Complex Math Unit (VCU-II)
    • 16 x 16 and 32 x 32 MAC Operations
    • 16 x 16 Dual MAC
    • Three 32-Bit CPU Timers per Core
  • Two Programmable Control Law Accelerators (CLAs)
    • 200 MHz (5-ns Cycle Time)
    • 32-Bit Floating-Point Math Accelerator
  • On-Chip Memory
    • Up to 1MB Flash, Up to 204KB RAM
    • Boot ROM (64KB)
  • System Peripherals
    • Dual 32- and 16-Bit EMIF With ASRAM and SDRAM Support
    • Dual 6-Channel DMA Controller
    • Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering
  • Communications Peripherals
    • USB 2.0 + PHY Port
    • Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface
    • Two CAN-Bus Ports (32 Mailboxes Each)
    • Three High-Speed (40-MHz) SPI Ports With 16-Level FIFO, DMA Support, and
      CLA-Accessible
  • Analog Subsystem
    • Four Dual-Mode Analog-to-Digital Converters (ADCs)
    • 16-Bit Mode
    • 12-Bit Mode
    • Single Sample-and-Hold (S/H)
      (Four-Simultaneous-S/H System)
    • Integrated Post-Processing of ADC Conversions
    • Analog Comparator/Digital-to-Analog Converter (DAC) Subsystem With Glitch Filter, for Windowed Trip Monitor and PCMC Interfaces
    • Three 12-Bit Buffered DAC Outputs
  • Enhanced Control Peripherals
    • 24 PWM Channels With Enhanced Features
    • 16 High-Resolution PWM Channels
    • Six Enhanced Capture (eCAP) Modules
    • Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Two Sigma-Delta Filter Modules With up to 8 Input Channels, and PWM Synchronization
  • Expanded Peripheral Interrupt (ePIE) Block
    • Supports up to 192 Peripheral Interrupts
    • GPIO Pins can be Connected to 5 Core Interrupts
  • JTAG Boundary Scan Support(1)
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Two Hardware Breakpoints per CPU
    • Real-Time Debug via Hardware
  • Independent Dual-Zone Security per CPU
    • 128-Bit Security Key and Lock
    • Protects Flash, One-Time Programmable (OTP) Memory, and RAM Blocks
  • Safety and Reliability Features
    • Error Correction Code (ECC) on Flash, ECC or Parity on RAMs
    • Missing Clock Detection
    • Hardware Built-In Self-Test (for CPUs)
    • Programmable Built-In Self-Test (for Memory)
  • Low-Power Modes and Power Savings
    • IDLE, STANDBY, HALT, and HIBERNATE Modes Supported
    • Disable Individual Peripheral Clocks
  • Clock and System Control
    • Two Internal Zero-Pin 10-MHz Oscillators
    • On-Chip Crystal Oscillator/External Clock Input
  • 1.2-V Core, 3.3-V I/O Design
  • Development Support Includes
    • ANSI C/C++ Compiler/Assembler/Linker
    • Code Composer Studio IDE
    • DSP/BIOS and SYS/BIOS
    • Digital Motor Control and Digital Power Libraries
  • Package Options:
    • Lead-Free, Green Packaging
    • 337-Ball New Fine Pitch Ball Grid Array (nFBGA) [ZWT Suffix]
    • 176-Pin PowerPAD Thermally Enhanced Low-Profile Quad Flatpack
  • Temperature Options