The PowerPC 440SPe Processor offers a powerful mix of high bandwidth, design flexibility and robust features, with speeds of up to 667MHz. With PCI Express and PCI-X interfaces, an on-chip DDR I/DDR II SDRAM controller, I2O messaging unit, XOR accelerator unit, and a rich peripheral mix, the PowerPC 440SPe processor is ideally suited for RAID controllers, Storage Area Networking (SAN) equipment and other embedded storage and networking applications.

Highlights

• Delivers 533MHz to 667MHz performance for embedded I/O processor designs
• 32K-I/32K-D L1 caches
• 256K L2 cache, may also be used as on-chip SRAM
• High-speed Processor Local Bus (PLB) with 2-way crossbar, supports 10.4GB/sec. peak bandwidth
• Three PCI Express interfaces
• PCI-X Interface Supports DDR Operation
• Dual-ported 32/64-bit SDRAM memory controller, interfaced to both PLB slave segments, supporting 166/333MHz DDR I and 333/667MHz DDR II
• Built-in XOR function for parity generation and checking; one-channel DMA capability
• Integrated I2O messaging with two-channel DMA capability
• State-of-the-art on-chip peripherals including 10/100/1000 Ethernet MAC, UARTs, IIC
• Offers low power dissipation and small form factor for high-density and power-conscious applications

The PowerPC 440 Core

To enhance overall throughput, the PowerPC 440 superscalar core incorporates a 7-stage pipeline and executes up to two instructions per cycle. Its large 32KB data cache and 32KB instruction cache are 64-way set-associative. Versatile configurations enhance performance tuning while optional parity protection preserves data integrity. For additional system performance, the PowerPC 440 core includes dynamic branch prediction and 24 digital signal processing (DSP) instructions, as well as nonblocking caches that can be managed in either write-through or write-back mode.

Features

• 533 to 667MHz, 1,334 DMIPS @ 667MHz
• 32K-I/32K-D L1 caches, and 256K L2/SRAM with parity protection
• 32/64-bit DDR I/DDR II SDRAM Controller, for DDR166/333 and DDR333/667 operation
• Three PCI Express Interfaces, one with eight lanes configurable as x8, x4, x1 and two with four 4 lanes configurable as x4, x1; 2.5 Gbps full duplex per lane; Compliant with PCI Express base specification 1.0a; configurable as root or end point
• 64-bit PCI-X version 2.0 3.3v interface, up to 133MHz / DDR266; 1.6GBps sustained bandwidth, 2.13GBps peak bandwidth; Support for PCI-X v1.0a up to 133MHz and PCI v2.3, up to 66MHz
• Opaque PCI Epress to PCI Express, and PCI Express to PCI-X bridge functionality
• Ability to boot from the primary PCI-X bus memory
• XOR core accelerates parity generation and check functions
• Intelligent Messaging Unit (I2O specification)
• Two-channel DMA included with I2O, One-channel DMA included with XOR
• External Bus Control (EBC) Interface (up to 83MHz) supporting up to three ROM, RAM, or EPROM peripheral devices
• One 10/100/1000 Mbps Ethernet MAC, full duplex GMII/MII interface with DMA capability via Memory Access Layer (MAL)
• Three serial ports (16750 compliant UARTs) with 64 byte FIFOs
• Two IIC controllers
• Up to 32 General Purpose I/Os (GPIO)
• General purpose timers
• Universal Programmable Interrupt Controller supports 16 external interrupt sources and 101 internal sources
• JTAG, RISCTrace� and RISCWatch� support

High-Bandwidth Bus Architecture

The PowerPC 440SPe CoreConnect 128-bit Processor Local Bus (PLB) provides a two-way crossbar, with a separate 128-bit read and 128-write data bus for each way. The four 128-bit data buses may operate concurrently, providing up to 10.4GBps of peak onchip bandwidth at 166MHz. The SDRAM is attached to two PLB slave ways to provide optimal access to memory from any other peripheral/core. The 440 core's 36-bit address path, provides 64GB memory addressability, while the PLB offers 64-bit addressability to support the PCI Express and PCI-X cores. Lower bandwidth I/O devices are supported by the On-Chip Peripheral Bus (OPB).

High Performance Memory Support

The 440SPe incorporates a high-performance DDR memory controller supporting DDR I and DDR II memory devices. With the DDR II operation, the memory interface can operate at an effective rate of DDR667, for a maximum bandwidth of 5.32GBps. The interface can be configured for 64-bit or 32-bit memory implementations, with optional ECC. Industry standard DIMMS and discrete devices are supported with up to four banks, allowing for for up to 16GB of memory (peak DDR667 performance can be achieved when two memory banks are used). For greater efficiency, the memory controller provides parallel paths from each of the PLB slave segments and memory.

PCI Express and PCI-X Interfaces

The 440SPe offers three independent PCI Express interfaces compliant with PCI Express base specification 1.0a. The primary or host PCI Express interface has eight lanes and supports x8, x4 or x1 configurations. The two secondary or local PCI Express interfaces have four (4) lanes each and support x4 or x1 configurations. Each lane operates at 2.5 Gbps full duplex. All three PCI Express interfaces can be configured as root or end point ports.

In addition to the three PCI Express interfaces, the 440SPe includes one 64-bit PCI-X version 2.0 interface, which operate at double data rate (DDR), latching data on both edges of the clock for an effective DDR266 throughput. The PCI-X interface offers a peak bandwidth of 2.13GBps, is compatible with PCI-X v1.0a and PCI v2.3 specifications, and includes an internal arbiter. This interface may be configured in Host or Adapter mode.

The PCI Express and PCI-X interfaces can function as an opaque PCI bridge. After initial configuration, data may be transferred directly between two PCI Express interfaces or between a PCI Express and a PCI-X interface without 440SPe processor involvement, freeing the processor to perform other tasks.

Ethernet Interface

A 10/100/1000 Mbps Ethernet MAC (EMAC) provides a full-duplex GMII/MII interface with packet reject capability. In RAID controller applications this EMAC is intended to be used mainly as a management port.

XOR and I2O Accelerate Storage Applications

The 440SPe offers an on-chip XOR accelerator unit to perform parity generation and check functions across data stripes. The benefit of this approach is two-fold. Not only is the XOR accelerator able to perform these functions much faster than a general purpose CPU, but by offloading this work from the main processor, processor cycles are reserved for other functions. I/O processing and other applications using multiple processors can benefit from the integrated messaging unit. Using I2O message frames, this messaging unit improves system performance by enabling the 440SPe to communicate with a host system on the host-side PCI Express bus. This allows the 440SPe to work as an intelligent I/O adapter controller. For greater performance, two DMA hardware controllers work with the XOR and I2O units to support memory-to-memory transfers. The first controller offers one-channel DMA to the the XOR accelerator, while the second one provides two-channel DMA to the I2O functional block.

Standard Peripherals

Two IIC controllers, compliant with Philips I2C specification, operate at 100/400KHz. Both support master mode with multimaster and reset and target mode, and one supports serial boot ROM. The peripheral set also includes three UARTs, up to 32 general purpose I/Os (GPIO) and general purpose timers.

Development Tools Support

PowerPC embedded processors are supported by AMCC and more than one hundred third-party vendors through the PowerPC Embedded Tools program. This program provides compilers, debuggers, real-time operating systems, emulators, logic analyzers, and a full range of tools to help manufacturers develop products more quickly. A PowerPC 440SPe reference board kit is available to help expedite product evaluation and project development.