Advanced technology for Imaging and Industrial Control applications

General Description

The PowerPC 440EP embedded processor offers exceptional performance, design flexibility, and robust features geared to demanding Imaging, industrial control, networking and other embedded applications. With speeds of up to 533MHz, PowerPC Book E Architecture, and a rich peripheral mix, PowerPC 440EP processors are ideally suited for a wide range of high-performance applications.

AMCC's advanced 0.13-micron CMOS copper process technology and an innovative design provide low power dissipation and a small footprint. Application code compatibility with other PowerPC processors enables manufacturers to bring products to market quickly and at a low cost to satisfy changing needs. High integration with robust peripheral support can further simplify board design and help reduce manufacturing costs.

Highlights

• Delivers 333MHz to 533MHz performance for high-speed embedded designs
• 32-bit implementation of the Book E Enhanced PowerPC® Architecture
• Superscalar PowerPC 440 core, with large L1 caches, with the high-speed IBM CoreConnec- bus technology
• Single/double-precision floating point unit
• State-of-the-art peripherals including DDR SDRAM, and extensive connectivity via Ethernet, USB, UARTs, IIC, SPI and PCI
• Offers low power dissipation and small form factor for high-density and power-conscious applications
• Provides application code compatibility with other PowerPC processors

Features

• 440 core and DDR interface connect to CoreConnect PLB4
• 100-133MHz, 128-bit data read and write buses, 36-bit address bus
• Performance monitor
• Bridge to PLB3, 100-133MHz, for PCI, EBC, Ethernet, and OPB peripherals
• On-chip Double Data Rate (DDR) SDRAM controller
• 32-bit interface with optional ECC
• 13-bit addressing
• 1.1 GBps peak data rate
• Support for 4 banks of up to 256MB, maximum capacity of 1GB
• Support for 64, 128, 256, and 512Mb DDR devices, with CAS latencies of 2, 2.5, or 3
• PCI interface
• 32-bit PCI V2.2, with 3.3V interface, at frequencies of up to 66MHz
• Multiple read prefetch and write post buffers
• Ability to boot processor from PCI bus memory
• USB
• USB 1.1 host, MAC and PHY
• USB 2.0 Device MAC
• USB 2.0 device MAC UTMI or USB 1.1 device PHY–device supports 6 end points (3 in, 3 out), 1024 Byte FIFO (double buffering of 512 byte packets)
• FPU
• 5 stage FPU with 2.0 MFLOPS/MHz (SP/DP)
• Hardware support for IEEE 754
• Single-precision and double-precision operation
• Single cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
• External bus controller
• 50-66MHz
• 8-bit or 16-bit external data bus width
• Up to 30-bit address bus
• Support for up to 6 ROM, EPROM, SRAM, Flash, or slave peripheral I/O devices
• External master support
• Nand Flash controller
• Block-oriented device, accessed in a manner much like diskette drives with pages, blocks, and, in some devices, zones or districts
• 1 to 4 banks of Nand Flash supported on EBC
• Direct interfacing to: Discrete Nand Flash devices (up to 4 devices) and SmartMedia Card socket (22-pins)
• Device sizes 4MB-256MB supported
• 512-byte + 16-byte or 2KB + 64-byte device page sizes supported
• Boot-from-Nand: Execute a linear sequence of boot code out of single page of 1st block (512- bytes)
• Support DMA to allow direct, no-processor-intervention block copy from Nand Flash out to SDRAM - ECC providing single bit error correction and double bit error detection in each 256-bytes of stored data
• Chip selects shared with EBC
• DMA controller
• 4 independent channels supporting internal and external peripherals