The Stellaris® LM3S5757 microcontroller is based on the ARM® Cortex™-M3 controller core operating at 50 MHz, with 128 kB single-cycle flash, 64 kB single-cycle SRAM, a 32-ch DMA, a CAN controller, USB On-The-Go/Host/Device, a 24-bit Systick Timer, 3x 32-bit or 6x 16-bit general-purpose timers, a watchdog timer, two SSI / SPI controllers, two I2C interfaces, a UART, a 10-bit analog-to-digital converter (ADC) with 8 input channels (+/- 1 LSb of accuracy), a battery-backed hibernation module with RTC and 256 bytes of non-volatile state-saving memory, a low drop-out voltage regulator, brown-out reset, power-on reset controller, and up to 61 GPIOs.  Furthermore, the LM3S5757 microcontroller features ROM preloaded with the Stellaris Driver Library and BootLoader.

Product features

32-Bit RISC Performance

• 50-MHz operation with 32-bit ARM® Cortex™-M3 architecture
• Thumb®-compatible Thumb-2-only instruction set, with hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling
• 28 interrupt channels with eight priority levels
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality
• Unaligned data access enables data to be efficiently packed into memory
• Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control

On-Chip Memory

• 128 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
  • User-managed flash block protection on a 2-KB block basis
  • User-managed flash data programming
  • User-defined and managed flash-protection block
• 64 KB single-cycle SRAM
• Pre-programmed ROM containing the Stellaris® family peripheral driver library (DriverLib) and Stellaris® boot loader

DMA Controller

• Developed and tested by ARM
• Up to a maximum of 32 configurable DMA channels, each with dedicated handshake signals and configurable priority levels
• Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers
• Supports DMA transfers using data widths of 8, 16, or 32-bits
• Supports USB, UART, and SSI
• Compatible with the AMBA AHB-Lite protocol
• Number of transfers in each DMA cycle is programmable in binary steps from 1 to 1024
• Each DMA channel has separate outputs to indicate when a DMA cycle is active or complete

Controller Area Network (CAN)

• Supports CAN protocol version 2.0 A/B
• 32 message objects, each with its own identifier mask
• Bit rates up to 1Mb/s
• Disable automatic retransmission mode for TTCAN
• Maskable interrupt
• Programmable loop-back mode for self-test operation

UART

• Fully programmable 16C550-type UART
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator allowing speeds up to up to 3.125 Mbps

USB

• Standards-based universal serial bus controller
• USB 2.0 full-speed (12 Mbps) operation
• Flexible configuration option
  • USB Device mode
  • USB Host mode
  • USB On-The-Go (OTG) mode
• Integrated PHY
• 4 transfer types: Control, Interrupt, Bulk, and Isochronous
• 1 dedicated bi-directional control endpoint
• 3 Receive and 3 Transmit configurable endpoints
• 2 KB dedicated endpoint memory
  • Direct memory access (DMA)
  • One endpoint may be defined for double-buffered 1023-byte isochronous packet size

Analog-to-Digital Converter (ADC)

• Single- and differential-input configurations
• Eight 10-bit channels (inputs) when used as single-ended inputs
• Sample rate of 500 thousand samples/second
• On-chip temperature sensor

Inter-Integrated Circuit (I2C) Interface

• Two I2C modules
• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

GPIOs

• 25-61 GPIOs, depending on configuration
• 5-V-tolerant input/outputs
• Programmable interrupt generation as either edge-triggered or level-sensitive
• Low interrupt latency; as low as 6 cycles and never more than 12 cycles
• Bit masking in both read and write operations through address lines
• Can initiate an ADC sample sequence

Power

• On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Battery-backed hibernation module with real-time clock and 256-bytes of non-volatile memory
• Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits
• Low-power options on controller: Sleep and Deep-sleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• On-chip temperature sensor

Flexible Reset Sources

• Power-on reset (POR)
• Reset pin assertion
• Brown-out (BOR) detector alerts to system power drops
• Software reset
• Watchdog timer reset
• Internal low drop-out (LDO) regulator output goes unregulated

Additional Features

• Programmable clock source control
• Clock gating to individual peripherals for power savings
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• Full JTAG boundary scan

Package and Temperature

• 100-pin RoHS-compliant LQFP package
  • Industrial-range (-40°C to +85°C)