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MPC8540
Order Information
United States
Addressing the needs for higher compute density and lower system cost, Freescale Semiconductor´s MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Freescale´s first device utilizing the e500 core; is the industry´s first RapidIO-enabled processor; and provides dual gigabit ethernet controllers. Balancing processor performance with I/O system throughput, the MPC8540 is a powerful control element for network routers and switches, storage subsystems, network appliances, and print and imaging devices.
Innovative Technology
The MPC8540 processor integrates IEEE 802.3 10/100/1G Ethernet controllers (with support for jumbo frames and Layer 2 acceleration), a 10/100 controller, a 64-bit PCI-X controller operating at up to 133 MHz, a DDR memory controller, a 4-channel DMA, a multi-channel interrupt controller, and a DUART serial interface. Its high level of integration means simplified board design, lower power consumption and a faster time-to-market solution for customers.
The MPC8540 also integrates the e500 core, 256 KB of on-chip L2 cache, and the revolutionary on-chip non-blocking crossbar switch fabric, called OCeaN (On-Chip Network), providing cross-sectional bandwidth of up to 22 Gbps peak bandwidth per port together with independent transaction queuing and flow control.
e500 Core
Utilizing an SoC platform which balances MIPs, watts, packet performance and cost, Freescale has created a flexible platform architecture enabling multiple products from easily integrated IP. The e500 high performance core implements the enhanced PowerPC Book E instruction set architecture and provides unprecedented levels of hardware and software debug support. The e500 will serve as the core for a family of ASSPs for communications, automotive and consumer applications.
RapidIO Interconnect
As a founding member of the RapidIO Trade Association, Freescale has been driving the industry adoption of this new, high-performance switch fabric control plane interconnect. RapidIO offers significantly greater bandwidth, scalability and reliability than interconnects used today, yet is compatible with existing PCI and CPU architectures. It has a flexible architecture that can easily adapt to changing industry needs without affecting existing infrastructure. RapidIO is an open standard governed by an industry body, designed specifically for embedded, networking and communications applications.
Features
Embedded e500 Book E compatible core available from 600 MHz up to 1 GHz
- 32-bit, dual-issue, superscalar, seven-stage pipeline
- 1850 MIPS at 800 MHz (est. Dhrystone 2.1)
- 32 KB L1 data and 32 KB L1 instruction cache with line locking support
- 256 KB on-chip L2 cache with direct mapped capability
- Enhanced hardware and software debug support
- Memory management unit (MMU)
- SIMD extension with single precision floating point
- Two triple-speed Ethernet controllers (TSECs) supporting 10/100/1000 Mbps Ethernet (IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII interfaces
- 166 MHz, 64-bit, 2.5V I/O, DDR SDRAM memory controller with full ECC support
- 500 MHz, 8-bit, LVDS I/O, RapidIO controller
- 133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 bus controller
- 166 MHz, 32-bit, 3.3V I/O, local bus with memory controller
- 10/100 Ethernet controller (802.3) for chip debug and maintenance support
- Integrated four-channel DMA controller
- Interrupt controller
- IEEE 1149.1 JTAG test access port
- 1.2V core power supply with 3.3V and 2.5V I/O
- 783-pin FC-BGA package
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