The Stellaris® LM3S6918 microcontroller is based on the ARM® Cortex™-M3 controller core operating at 50 MHz, with 256 kB single-cycle flash, 64 kB single-cycle SRAM, 10/100 Ethernet MAC/PHY, a 24-bit Systick Timer, 4x 32-bit or 8x 16-bit general-purpose timers, a watchdog timer, two SSI / SPI controllers, two I2C interfaces, 2 UARTs, 2 analog comparators, a 10-bit analog-to-digital converter (ADC) with 8 input channels (+/- 1LSb of accuracy), a battery-backed hibernation module with RTC and 256 bytes of non-volatile state-saving memory, a low drop-out voltage regulator, brown-out reset, power-on reset controller, and up to 38 GPIOs.
Product Features
32-Bit RISC Performance
32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
50-MHz operation with 32-bit ARM® Cortex™-M3 architecture
System timer (SysTick) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
Thumb®-compatible Thumb-2-only instruction set, with hardware-division and single-cycle-multiplication
Memory protection unit (MPU) provides a privileged mode for protected operating system functionality
Unaligned data access enables data to be efficiently packed into memory
Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control
On-Chip Memory
256 KB single-cycle flash
User-managed flash block protection on a 2-KB block basis
User-managed flash data programming
User-defined and managed flash-protection block
64 KB single-cycle SRAM
Flexible Timer Capability
Four general-purpose timers, each configurable as one 32-bit or two 16-bit timers
Real-Time Clock (RTC) capability
24-bit system (SysTick) timer
32-bit watchdog timer
General-Purpose Timers
Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timer/counters. Each GPTM can be configured to operate independently as timers or event counters (eight total): as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC) to event capture, for Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions
32-bit Timer modes
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug
ADC event trigger
16-bit Timer modes
General-purpose timer function with an 8-bit prescaler
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
ADC event trigger
16-bit Input Capture modes
Input edge count capture
Input edge time capture
16-bit PWM mode
Simple PWM mode with software-programmable output inversion of the PWM signal
Watchdog Timer
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
10/100 Ethernet Controller
Conforms to the IEEE 802.3-2002 Specification
IEEE 1588-2002 Precision Time Protocol (PTP) compliant
Full- and half-duplex for both 100 Mbps and 10 Mbps operation
Integrated 10/100 Mbps Transceiver (PHY)
Automatic MDI/MDI-X cross-over correction
Programmable MAC address
Power-saving and power-down modes
Serial Interfaces
Two synchronous serial interfaces (SSI) with master and slave modes for SPI, MICROWIRE, or TI synchronous serial
Two I2C interfaces (master and slave)
Two fully programmable 16C550-type UARTs with IrDA support
Synchronous Serial Interface (SSI)
Two SSI modules, each with the following features:
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
UART
Two fully programmable 16C550-type UARTs with IrDA support
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
Programmable baud-rate generator with fractional divider
Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
False-start-bit detection
Line-break generation and detection
Analog-to-Digital Converter (ADC)
Single- and differential-input configurations
Eight 10-bit channels (inputs) when used as single-ended inputs
