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Renesas Electronics

V850 » UPD70F3366GJ(A)-UEN-A

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The V850ES/SG3 are 32-bit single-chip microcontrollers that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. The V850ES/SG3 and V850ES/SJ3 includes an IEBus ® (Inter Equipment Bus ®) controller for the automotive LAN, and some of the models also include a CAN (Controller Area Network) controller.

Key Features:


  • Max Frequency: 32 MHz
  • Operating Voltage: 2.85 to 3.6 V
  • ROM Size: 256 to 1024 KB Flash
  • RAM Size: 24 to 60 KB
  • Package: 100-pin plastic LQFP (fine pitch) (14 x 14), 144-pin plastic LQFP (fine pitch) (20 x 20)
  • Minimum instruction execution time: 31.25 ns (operating with main clock (fXX) of 32 MHz)
  • General-purpose registers: 32 bits x 32 registers
  • CPU features:
    • Signed multiplication (16 x 16 -> 32): 1 to 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operations (overflow and underflow detection functions included)
    • 32-bit shift instruction: 1 clock
    • Bit manipulation instructions
    • Load/store instructions with long/short format
  • Memory space:
    • 64 MB of linear address space (for programs and data)
    • External expansion: Up to 4 MB
    • External bus interface: Separate bus/multiplexed bus output selectable
    • 8/16 bit data bus sizing function
    • Wait function (Programmable wait function / External wait function)
    • Idle state function
    • Bus hold function
  • Interrupts and exceptions:
    • Non-maskable interrupts: 2 sources
    • Maskable interrupts: 59 sources (V850ES/SG3) / 73/77 sources (V850ES/SJ3)
    • Software exceptions: 32 sources
    • Exception trap: 2 sources
  • I/O ports: 84 (V850ES/SG3) / 128 (V850ES/SJ3)
  • Timer function:
    • 16-bit interval timer M (TMM): 1 channel
    • 16-bit timer/event counter P (TMP): 6 channels (V850ES/SG3) / 9 channels (V850ES/SJ3)
    • 16-bit timer/event counter Q (TMQ): 1 channel
    • Watch timer: 1 channel
    • Watchdog timer: 1 channel
  • Real-time output port: 6 bits × 1 channel
  • Serial interface:
    • Asynchronous serial interface A (UARTA)
    • 3-wire variable-length serial interface B (CSIB)
    • I2C bus interface (I2C)
    • UARTA/CSIB: 1 channel
    • UARTA/I2C: 2 channels
    • CSIB/I2C: 1 channel
    • CSIB: 3 channels (V850ES/SG3) / 4 channels (V850ES/SJ3)
    • IEBus controller: 1 channel
    • CAN controller: 1 channel (V850ES/SG3 CAN controller versions only) / 1/2ch (V850ES/SJ3 CAN controller versions only)
  • A/D converter: 10-bit resolution x 12 channels (V850ES/SG3) / 10-bit resolution x 16 channels (V850ES/SG3)
  • D/A converter: 8-bit resolution: 2 channels
  • DMA controller: 4 channels
  • CRC function: 16-bit error detection codes are generated for data in 8-bit units
  • Debug control unit (DCU): JTAG interface
  • ROM correction: 4 correction addresses specifiable
  • Clock generator:
    • During main clock or subclock operation
    • 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
    • Clock-through mode/PLL mode selectable
    • Internal oscillation clock: 220 kHz (TYP.)
  • Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
  • Data Sheet

    V850ES/SG3