The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, communication, and automotive markets. To optimize system power consumption, the LPC2917/2919/01 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.

Features

• ARM968E-S processor at 125 MHz maximum
• Multi-layer AHB system bus at 125 MHz with three separate layers
• On-chip memory:
  • Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM (DTCM)
  • Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB SRAM
    
  • Up to 768 kB flash-program memory
• Two-channel CAN controller supporting Full-CAN and extensive message filtering
• Two LIN master controllers with full hardware support for LIN communication
• Two 550 UARTs with 16-byte Tx and Rx FIFO depths
• Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO
• Four 32-bit timers each containing four capture-and-compare registers linked to I/Os
• 32-bit watchdog with timer change protection, running on safe clock.
• Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus keeper
• Vectored Interrupt Controller (VIC) with 16 priority levels
• Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion times as low as 2.44 μs per channel. Each channel provides a compare function to minimize interrupts
• Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up features
• External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus
• Processor wake-up from power-down via external interrupt pins; CAN or LIN activity
• Flexible Reset Generator Unit (RGU) able to control resets of individual modules
• Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules
  • On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring
  • On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL input 15 MHz
  • On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz
  • Generation of up to 10 base clocks
  • Seven fractional dividers
• Highly configurable system Power Management Unit (PMU),
  • clock control of individual modules
  • allows minimization of system operating power consumption in any configuration
• Standard ARM test and debug interface with real-time in-circuit emulator
• Boundary-scan test supported
• Dual power supply:
  • CPU operating voltage: 1.8 V ± 5%
  • I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V
• Two package variants: 100-pin LQFP and 144-pin LQFP package
• −40 °C to 85 °C ambient operating temperature range