Product Overview:

The H8S/2378 Group and H8S/2378R Group microcomputers (MCU) made up of theH8S/2000 CPU employing Renesas Technology´s original architecture as their cores, and the peripheral functions required to configure a system.
TheH8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation.The H8S/2000 CPU can handle a 16-Mbyte linear address space.
This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system configuration. I2C bus interface 2(IIC2)can also be included as an optional interface.
A high functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory.
A single-power flash memory (FLASH) version is available for this LSI´s ROM. The FLASH version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

Key Features:

• Operating frequency (MHz)/Supply voltage (V)
  • 33MHz/3.0V to 3.6V
    • Minimum instruction execution time: 30ns
• On-chip memory
  • 512kB/32kB：H8S/2378BF, H8S/2378RF
  • 384kB/32kB : H8S/2374RF, H8S/2374F*
  • 384kB/24kB：H8S/2377F, H8S/2377RF
  • 256kB/32kB：H8S/2372RF, H8S/2372F*
  • 256kB/24kB：H8S/2371RF, H8S/2371F*
  • 256kB/16kB：H8S/2370F, H8S/2370RF
  • 256kB/16kB：H8S/2375 , H8S/2375R　
  • - /16kB：H8S/2373 , H8S/2373R

                 Note: *Includes Synchronous DRAM support.

• Internal SDRAM interface :
  • H8S/2378R 0.18μm F-ZTAT group*2、
  • H8S/2377RF、H8S/2375R、H8S/2373R
• On chip debugger(support E10A-USB)
  • H8S/2378 0.18μm F-ZTAT group*1
  • H8S/2378R 0.18μm F-ZTATgroup *2

Key Applications:

TV Digital TV, Game Music Instruments, Remote Controller, Office automationequipment, PC Peripherals(External memory, Input, Output, Monitor),Communication equipment Telephone, home information appliances, and Digital consumer applications

Built-in Functions 

• High-speed H8S/2000 central processing unit with 16-bit architecture
  • Upward-compatible with H8/300 and H8/300H CPUs on an object level
  • Sixteen 16-bit general registers
  • 65 basic instructions
  • Address space: 16M byte
• Interrupt
  • Internal: 64: H8S/2378R, 2378A, 2377R, 2377
  • Internal: 57: H8S/2376
  • Internal: 62: H8S/2375R, 2375, 2373R, 2373
  • External:17
• Bus controller
  • External data bus width: 8/16 bits
• Variious peripheral functions
  • DMA controller (DMAC) x 4ch Note: Not supported by the H8S/2376.
  • EXDMA controller (EXDMAC) Note: Not supported by the H8S/2376, H8S/2375, H8S/2375R, H8S/2373,H8S/2373R.
  • Data transfer controller (DTC) x 85ch
  • 16-bit timer-pulse unit (TPU) x 6ch
  • Programmable pulse generator (PPG) x 16ch Note: Not supported by the H8S/2376.
  • 8-bit timer (TMR) x 2ch
  • Watchdog timer (WDT) x 1ch
  • Asynchronous or clocked synchronous serial communication interface (SCI) x5ch
  • I2C bus interface 2 (IIC2) x 2ch
  • 10-bit A/D converter x 16ch
  • 8-bit D/A converter
    • x 6ch: H8S/2378R, 2378A, 2377R, 2377
    • x 4ch: H8S/2376
    • x 2ch: H8S/2375R, 2375, 2373R, 2373
  • Clock pulse generator
  • User debug interface: H8S/2378R, 2378A, 2377R, 2377
  • Internal SDRAM interface: H8S/2378R Group
• General I/O ports
  • I/O pins: 97
  • Input-only pins: 16

Hardware Manuals

H8S/2378R

Quick HEW Demonstration

HEW Installation and Administration

H8S Family Overview

H8S Architecture Overview