The LM3S102 is a high-performance ARM® Cortex™-M3 v7M architecture microcontroller is designed for cost-sensitive applications. It is fully Thumb®-compatible with a Thumb-2-only instruction set and features hardware-division and single-cycle-multiplication. We also managed to squeeze in an Integrated Nested Vectored Interrupt Controller (NVIC) to provide deterministic interrupt handling. Target applications include factory automation and control, industrial control power devices, and building and home automation.

Features

• 32-bit ARM® Cortex™-M3 v7M architecture
• Thumb®-compatible Thumb-2-only instruction set
• 20 MHz operation
• Hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling
• 14 interrupt channels with eight priority levels
• 8 kB single-cycle flash with two forms of flash protection on a 2 KB block basis
• 2 kB single-cycle SRAM
• Two timers
  • Each can be configured as a single 32-bit timer or as a dual 16-bit timer
  • One supports capture and simple PWM modes
  • Real-Time Clock (RTC) capability
• Separate watchdog timer
• Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE, or Texas Instruments synchronous serial
• Fully programmable 16C550-type UART
• Integrated analog comparator
  • Configurable for output to drive an output pin or generate an interrupt
  • Compare external pin input to external pin input or to internal programmable voltage reference
• I2C master/slave transmit and receive operation with transmission speed up to 100 kbps in Standard mode and 400 kbps in Fast mode
• Up to 18 GPIOs, depending on user configuration
• Programmable GPIO interrupt generation as either edge-triggered or level-sensitive on all pins
• Programmable control for GPIO pad configuration:
  • Weak pull-up or pull-down resistors
  • 2 mA, 4 mA, and 8 mA pad drive
  • Slew rate control for the 8 mA drive
  • Open drain enables
  • Digital input enables
• On-chip Linear Drop-Out (LDO) voltage regulator
• Low-power options on processor: Sleep and Deepsleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3 V supply brownout detection and reporting via interrupt or reset
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• 28-pin RoHS-compliant SOIC
• Commercial and industrial operating temperatures