The LM3S801 is based on the high-performance ARM® Cortex™-M3 v7M architecture. It is fully Thumb®-compatible with a Thumb-2-only instruction set and features hardware-division and single-cycle-multiplication. The integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling. Target applications include factory automation and control, industrial control power devices, building and home automation, and brushless DC and AC induction motors.

Product Features

• 32-bit ARM® Cortex™-M3 v7M architecture
• Thumb®-compatible Thumb-2-only instruction set
• 50-MHz operation
• Hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling
• 26 interrupt channels with eight priority levels
• 64 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
• 8 KB single-cycle SRAM
• Three timers, each of which can be configured as a single 32-bit timer or as a dual 16-bit timer with capture and simple PWM modes
• Real-Time Clock (RTC) capability
• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic with an enable/disable
• Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial
• Master or slave operation
• Two fully programmable 16C550-type UARTs
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator
• Three independent integrated analog comparators
• Configurable for output to drive an output pin or generate an interrupt
• Compare external pin input to external pin input or to internal programmable voltage reference
• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
• Six motion-control PWM outputs
• Each PWM generator block has one 16-bit counter, two comparators, a PWM generator, and a deadband generator
• Output control block with PWM output enable of each PWM signal
• Hardware position integrator tracks the encoder position
• Velocity capture using built-in timer
• Interrupt generation on index pulse, velocity-timer expiration, and direction change
• Up to 36 GPIOs, depending on user configuration
• Programmable interrupt generation
• Programmable drive strength and slew rate
• Bit-masking in both read and write operations through the address lines
• On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Low-power options on processor: Sleep and Deepsleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3-V supply brownout detection and reporting via interrupt or reset
• 48-pin RoHS-compliant LQFP
• Industrial operating temperature