The LM3S628 is based on the high-performance ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications. It is fully Thumb®-compatible with a Thumb-2-only instruction set and features hardware-division and single-cycle-multiplication. The integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling. Target applications include factory automation and control, industrial control power devices, and building and home automation.

Product Features

• 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
• Thumb®-compatible Thumb-2-only instruction set processor core for high code density
• 50-MHz operation
• Hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling
• 22 interrupt channels with eight priority levels
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality
• Unaligned data access
• 32 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
• 8 KB single-cycle SRAM
• Three timers, each of which can be configured: as a single 32-bit timer, as a dual 16-bit timer with capture and simple PWM modes, or to initiate an
• Real-Time Clock (RTC) capability
• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic with an enable/disable
• Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial
• Master or slave operation
• Two fully programmable 16C550-type UARTs
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator with fractional divider
• Single- and differential-input configurations
• Eight 10-bit channels (inputs) when used as singleended inputs
• Sample rate of one million samples/second
• Flexible, configurable analog-to-digital conversion
• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
• 9 to 28 GPIOs, depending on user configuration
• Programmable interrupt generation as either edgetriggered or level-sensitive on all pins
• Can initiate an ADC sample sequence
• Programmable drive strength and slew rate
• Bit-masking in both read and write operations
• On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Low-power options on processor: Sleep and Deepsleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3-V supply brownout detection and reporting via interrupt or reset
• On-chip temperature sensor
• Six reset sources
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• 48-pin RoHS-compliant LQFP
• Industrial operating temperature