The LM3S612 is based on the high-performance ARM® Cortex™-M3 v7M architecture. It is fully Thumb®-compatible with a Thumb-2-only instruction set and features hardware-division and single-cycle-multiplication. The integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling. Target applications include factory automation and control, industrial control power devices, building and home automation, and DC and stepper motors.
Product Features
32-bit ARM® Cortex™-M3 v7M architecture
Thumb®-compatible Thumb-2-only instruction set
50-MHz operation
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller
25 interrupt channels with eight priority levels
32 KB single-cycle flash
8 KB single-cycle SRAM
Three timers, each of which can be configured: as a single 32-bit timer, as a dual 16-bit timer, or to initiate an ADC event
Real-Time Clock (RTC) capability
32-bit down counter
Separate watchdog clock with an enable
Programmable interrupt generation logic
Lock register protection from runaway software
Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial
Master or slave operation
Two fully programmable 16C550-type UARTs
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
Programmable baud-rate generator
Single- and differential-input configurations
Two 10-bit channels (inputs)
Sample rate of 500 thousand samples/second
Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence
Compare external pin input to external pin input or to internal programmable voltage reference
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
Interrupt generation
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
Two motion-control PWM outputs
Each PWM generator block has one 16-bit counter, two comparators, a PWM generator, and a deadband generator
Output control block with PWM output enable of each PWM signal
Can initiate an ADC sample sequence
7 to 34 GPIOs, depending on user configuration
Programmable interrupt generation as either edgetriggered or level-sensitive on all pins
Can initiate an ADC sample sequence
Programmable drive strength and slew rate
Bit-masking in both read and write operations
On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
Low-power options on processor: Sleep and Deepsleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brownout detection and reporting via interrupt or reset
On-chip temperature sensor
IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
