The LM3S310 is based on the high-performance 32-bit ARM® Cortex™-M3 v7M architecture. This device offers six channel outputs from a powerful pulse-width-modulator module.

Target applications include factory automation and control, industrial control power devices, building and home automation, and brushless DC and AC induction motors.

Product Features

• 32-bit ARM® Cortex™-M3 v7M architecture
• Thumb®-compatible Thumb-2-only instruction set
• 25-MHz operation
• Hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling
• 24 interrupt channels with eight priority levels
• 16 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
• 4 KB single-cycle SRAM
• Three timers, each of which can be configured as a single 32-bit timer or as a dual 16-bit timer with capture and simple PWM modes
• Real-Time Clock (RTC) capability
• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic with an enable/disable Synchronous Serial Interface (SSI)
• Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial
• Master or slave operation
• Two fully programmable 16C550-type UARTs
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator
• Three independent integrated analog comparators
• Configurable for output to drive an output pin or generate an interrupt
• Compare external pin input to external pin input or to internal programmable voltage reference
• Six motion-control PWM outputs
• Each PWM generator block has one 16-bit counter, two comparators, a PWM generator, and a deadband generator
• Output control block with PWM output enable of each PWM signal
• 3 to 36 GPIOs, depending on user configuration
• Programmable interrupt generation as either edgetriggered or level-sensitive on all pins
• Programmable drive strength and slew rate
• Bit-masking in both read and write operations through the address lines
• On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Low-power options on processor: Sleep and Deepsleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3-V supply brownout detection and reporting via interrupt or reset
• Power-on reset (POR)
• Reset pin assertion
• Brown-out (BOR) detector alerts to power drops
• Software reset
• Watchdog timer reset
• Internal linear drop-out (LDO) regulator output goes unregulated
• Programmable clock source control
• Clock gating to individual peripherals for power savings
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• 48-pin RoHS-compliant LQFP
• Industrial operating temperature