Product Overview

The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 200 MIPS at 180 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160-kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash® into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.

Features

• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
  • DSP Instruction Extensions
  • ARM Jazelle® Technology for Java® Acceleration
  • 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
  • 200 MIPS at 180 MHz
  • Memory Management Unit
  • EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
  • Mid-level implementation Embedded Trace Macrocell™
• Additional Embedded Memories
  • 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
  • 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
• External Bus Interface (EBI)
  • Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
• LCD Controller
  • Supports Passive or Active Displays
  • Up to 16-bits per Pixel in STN Color Mode
  • Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
• USB
  • USB 2.0 Full Speed (12 Mbits per second) Host Double Port Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels
  • USB 2.0 Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
• Bus Matrix
  • Handles Five Masters and Five Slaves
  • Boot Mode Select Option
  • Remap Command
• Fully Featured System Controller (SYSC) for Efficient System Management, including
  • Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes
  • Clock Generator and Power Management Controller
  • Advanced Interrupt Controller and Debug Unit
  • Periodic Interval Timer, Watchdog Timer and Real-time Timer
  • Three 32-bit PIO Controllers
• Reset Controller (RSTC)
  • Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shutdown Controller (SHDWC)
  • Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
  • 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
  • 3 to 20 MHz On-chip Oscillator and two PLLs
• Power Management Controller (PMC)
  • Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
  • Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
  • Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
  • Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
  • 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
  • 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
  • Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
• Real-Time Timer (RTT)
  • 32-bit Free-running Backup Counter Running at Slow Clock
• Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
  • 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
  • Input Change Interrupt Capability on Each I/O Line
  • Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Nineteen Peripheral DMA (PDC) Channels
• Multimedia Card Interface (MCI)
  • Compliant with Multimedia Cards and SDCards
  • Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
• Three Synchronous Serial Controllers (SSC)
  • Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
  • I²S Analog Interface Support, Time Division Multiplex Support
  • High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
  • Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
  • Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interface (SPI)
  • 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counters (TC)
  • Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
  • Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two-wire Interface (TWI)
  • Master Mode Support, All Two-wire Atmel EEPROMs Supported
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
  • 1.08V to 1.32V for VDDCORE and VDDBU
  • 2.7V to 3.6V for VDDOSC and for VDDPLL
  • 2.7V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)
• Available in a 217-ball LFBGA RoHS-compliant Package