Product Overview

The AT91SAM7A3 is a member of a series of 32-bit ARM7® microcontrollers with an integrated CAN controller. It features a 256-Kbyte high-speed Flash and 32-Kbyte SRAM, a large set of peripherals, including two 2.0B full CAN controllers, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface. Built-in lock bits protect the firmware from accidental overwrite. The AT91SAM7A3 integrates a complete set of features facilitating debug, including a JTAG Embedded ICE interface, misalignment detector, interrupt driven debug communication channel for user configurable trace on a console, and JTAG boundary scan for board level debug and test. By combining a high-performance 32-bit RISC processor with a high-density 16-bit instruction set, Flash and SRAM memory, a wide range of peripherals including CAN controllers, 10-bit ADC, Timers and serial communication channels, on a monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications in the automotive, medical and industrial world.

Features

• Incorporates the ARM7TDMI ® ARM® Thumb® Processor
  • High-performance 32-bit RISC Architecture
  • High-density 16-bit Instruction Set
  • Leader in MIPS/Watt
• EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
• 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes
  • Single Cycle Access at Up to 30 MHz in Worst Case Conditions
  • Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
  • Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
  • 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities
• 32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed
• Memory Controller (MC)
  • Embedded Flash Controller, Abort Status and Misalignment Detection
  • Memory Protection Unit
• Reset Controller (RSTC)
  • Based on Three Power-on Reset Cells
  • Provides External Reset Signal Shaping and Reset Sources Status
• Clock Generator (CKGR)
  • Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
• Power Management Controller (PMC)
  • Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle Mode, Standby Mode and Backup Mode
  • Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
  • Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
  • Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
  • 2-wire UART and Support for Debug Communication Channel interrupt
• Periodic Interval Timer (PIT)
  • 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
  • 12-bit key-protected Programmable Counter
  • Provides Reset or Interrupt Signal to the System
  • Counter May Be Stopped While the Processor is in Debug Mode or in Idle State
• Real-time Timer (RTT)
  • 32-bit Free-running Counter with Alarm
  • Runs Off the Internal RC Oscillator
• Two Parallel Input/Output Controllers (PIO)
  • Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
  • Input Change Interrupt Capability on Each I/O Line
  • Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
• Shutdown Controller (SHDWC)
  • Programmable Shutdown Pin and Wake-up Circuitry
• Two 32-bit Battery Backup Registers for a Total of 8 Bytes
• One 8-channel 20-bit PWM Controller (PWMC)
• One USB 2.0 Full Speed (12 Mbits per Second) Device Port
  • On-chip Transceiver, 2376-byte Configurable Integrated FIFOs
• Nineteen Peripheral DMA Controller (PDC) Channels
• Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended Identifiers
  • 16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter
• Two 8-channel 10-bit Analog-to-Digital Converter
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
  • Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
  • Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interfaces (SPI)
  • 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• Three 3-channel 16-bit Timer/Counters (TC)
  • Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
  • Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two Synchronous Serial Controllers (SSC)
  • Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
  • I²S Analog Interface Support, Time Division Multiplex Support
  • High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• One Two-wire Interface (TWI)
  • Master Mode Support Only, All Two-wire Atmel EEPROM’s Supported
• Multimedia Card Interface (MCI)
  • Compliant with Multimedia Cards and SD Cards
  • Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies
  • Embedded 1.8V Regulator, Drawing up to 130 mA for the Core and the External Components, Enables 3.3V Single Supply Mode
  • 3.3V VDD3V3 Regulator, I/O Lines and Flash Power Supply
  • 1.8V VDD1V8 Output of the Voltage Regulator and Core Power Supply
  • 3V to 3.6V VDDANA ADC Power Supply
  • 3V to 3.6V VDDBU Backup Power Supply
• 5V-tolerant I/Os
• Fully Static Operation: Up to 60 MHz at 1.65V and 85°C Worst Case Conditions
• Available in a 100-lead LQFP Green Package