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Home » Freescale Semiconductor » Kinetis K50

  Kinetis K50 Processors
  List & Compare        
  Part number Family Manufacturer Core Variant Freq. Flash/ROM Package
 PK53X256CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524288  LQFP144
 PK53X256CLQ100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524288  144MAP
 PK53N512CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  LQFP144
 PK53N512CLQ100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  144MAP
 PK52N512CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  LQFP144
 PK52N512CLQ100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  144MAP
 PK51N512CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  LQFP144
 PK51N512CLQ100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  LQFP100
 PK51N256CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  262144  144MAP
 PK50N512CMD100  Freescale Kinetis  Freescale Semiconductor ARM Cortex-M4
 100MHz  524800  LQFP144
  

The K50 MCU family is pin-, peripheral- and software-compatible with other Kinetis microcontrollers and provides designers with an Analog Measurement Engine consisting of integrated operational and transimpedance amplifiers and high-resolution ADC and DAC modules. The family also features IEEE® 1588 Ethernet and hardware encryption, full-speed USB 2.0 On-The-Go with device charger detect capability and a flexible low-power segment LCD controller with support for up to 320 segments. Devices start from 128 KB of flash in 64 QFN packages extending up to 512 KB in a 144 MAPBGA package.

Key Features: 

Ultra Low-Power

  • 10 low-power modes with power and clock gating for optimal peripheral activity and recovery times. Stop currents of <500 nA, run currents of <200 µA/MHz, 4 µs wake-up from Stop mode
  • Full memory and analog operation down to 1.71V for extended battery life
  • Low-leakage wake-up unit with up to eight internal modules and sixteen pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes
  • Low-power timer for continual system operation in reduced power state

Flash, SRAM and FlexMemory

  • 128 KB-512 KB flash. Fast access, high reliability with four-level security protection
  • 64 KB-128 KB of SRAM FlexMemory: 2-4 KB of usersegmentable byte write/erase EEPROM for data tables/system data. EEPROM with over 10M cycles and flash with 70 µsec write time (brownouts without data loss/corruption). No user or system intervention to complete programming and erase functions and full operation down to 1.71V. In addition, FlexNVM from 32 KB-256 KB for extra program code, data or EEPROM backup

Mixed-Signal Capability

  • Up to two operational amplifiers allow signal filtering and amplification
  • Up to two transimpedance amplifiers optimized for converting current inputs into voltages that can be read by the ADC
  • Up to two high-speed 16-bit ADCs with configurable resolution. Single or differential output mode operation for improved noise rejection. 500 ns conversion time achievable with programmable delay block triggering
  • Up to two 12-bit DACs for analog waveform generation for medical applications baseline (glucometer, pulseoximeter)
  • Up to three high-speed comparators providing fast and accurate motor over-current protection by driving PWMs to a safe state
  • Up to two programmable gain amplifiers with x64 gain for small amplitude signal conversion
  • Analog voltage reference provides an accurate reference to analog blocks, ADC and DAC, and replaces external voltage references to reduce system cost

Performance

  • ARM Cortex-M4 core
  • 72 or 100 MHz, single-cycle MAC DSP+single instruction multiple data (SIMD) extensions
  • Crossbar switch enables concurrent multi-master bus accesses, increasing bus bandwidth

Timing and Control

  • Up to three FlexTimers with a total of 12 channels. Hardware dead-time insertion and quadrature decoding for motor control
  • Carrier modulator timer for infrared waveform generation in remote control applications
  • Four-channel 32-bit periodic interrupt timer provides time base for RTOS task scheduler or trigger source for ADC conversion and programmable delay block

Human-Machine Interface

  • Hardware touch-sensing interface with up to 16 inputs. Operates in all low power modes (minimum current adder when enabled). Hardware implementation avoids software polling method. High sensitivity level allows use of overlay surfaces up to 5 mm thick
  • Flexible, low-power LCD controller with up to 320 segments (40x8 or 44x4). LCD blink mode enables low average power while remaining in low-power mode. Segment fail detect guards against erroneous readouts and reduces LCD test costs. Frontplane/backplane reassignment provides pin-out flexibility easing PCB design and allows LCD configuration changes via firmware with no hardware re-work. Supports multiple 3V and 5V LCD panel sizes with fewer segments (pins) than competitive controllers and no external components. Unused LCD pins can be configured as other GPIO functions

Connectivity and Communications

  • IEEE 1588 Ethernet MAC with hardware time stamping provides precision clock synchronization for real-time industrial control
  • USB 2.0 On-The-Go (full speed). Device charge detect optimizes charging current/time for portable USB devices enabling longer battery life. Low-voltage regulator supplies up to 120 mA off chip at 3.3V to power external components from 5V input
  • Up to six UARTs with IrDA support including one UART with ISO7816 smart card support. Variety of data size, format and transmission/reception settings supported for multiple industrial communication protocols
  • Inter-IC Sound (I2S) serial interface for audio system interfacing
  • Up to three DSPI and two I2C

Reliability, Safety and Security

  • Hardware Encryption coprocessor for secure data transfer and storage. Faster than software implementations and with minimal CPU loading. Supports a wide variety of algorithms - DES, 3DES, AES, MD5, SHA-1, SHA-256
  • Memory protection unit provides memory protection for all masters on the cross bar switch, increasing software reliability
  • Cyclic redundancy check engine validates memory contents and communication data, increasing system reliability
  • Independent-clocked COP guards against clock skew or code runaway for fail-safe applications such as the IEC 60730 safety standard for household appliances
  • External watchdog monitor drives output pin to safe state external components if watchdog event occurs

External Peripheral Support

  • FlexBus external bus interface provides interface options to memories and peripherals such as graphics displays. Supports up to 6 chip selects and 2GB addressable space
  • Secure digital host controller supports SD, SDIO, MMC or CE-ATA cards for in-application software upgrades, media files or adding Wi-Fi support