The SH7619 is the first Renesas microprocessor to offer an on-chip IEEE802.3*2 compliant Media Access Controller (MAC*3) and a PHY transceiver, previously connected externally, in a single chip. These features simplify development of a 10/100 Mbps (megabit per second) Ethernet LAN connection function, and enable the number of component parts to be reduced. The SH2 CPU core has a maximum operating frequency of 125 MHz, enabling high-speed execution ofTCP/IP and similar protocol processing, and the implementation of high-performance systems.
Key Features:
High-performance single-chip RISC with SH-2 core
163 MIPS 125 MHz
Built-in 32-bit multiplier
Mixed instructions/data cache (16kB)- 4-way set associative type