• Power supply voltage: VDD = 1.8 to 5.5 V
• Max. frequency 20 MHz
• ROM capacities 64 KB to 256 KB flash memory
• RAM capacities 4 KB to 12 KB
• 64 pins FPBGA or QFP package
• Minimum instruction execution time can be changed from high speed (0.05 µs: @ 20 MHz operation with high speed system clock) to ultra low-speed (61 µs: @ 32.768 kHz operation with subsystem clock)
• General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
• On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
• Self-programming (with boot swap function/flash shield window function)
• On-chip debug function
• On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
• On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
• On-chip multiplier (16 bits × 16 bits)
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
• On-chip BCD adjustment
• I/O ports: 55 (N-ch open drain: 4)
• Timer: 10 channels
  - 16-bit timer: 8 channels
  - Watchdog timer: 1 channel
  - Real-time counter: 1 channel
• Serial interface
  - UART/CSI: 1 channel
  - UART/CSI/simplified I2C: 1 channel
  - UART (LIN-bus supported): 1 channel
  - I2C: 1 channel
• 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V): 8 channels
• Operating ambient temperature: TA = -40 to +85°C