Product Overview:

The H8S/2678 Series and H8S/2678R Series are microcomputers (MCU) made up of the H8S/2600 CPU employing Hitachi\'s original architecture as their cores, and the peripheralfunctions required to configure a system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.
This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and datatransfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system configuration.
A highfunctionality bus controller is also provided, enabling fast and easy connection of DRAM, SDRAM, and other kinds of memory.
A single-power flash memory (F-ZTAT™) version and masked ROM version are available for this LSI\'s ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable toapplication devices with specifications that will most probably change.

Key Features:

• Operating frequency (MHz)/Supply voltage (V)
  • 33MHz/3.0 to 3.6V
    • Minimum instruction-execution time: 30ns (33MHz/3.3V)
• On-chip memory
  • 256kB/8kB: H8S/2676
  • 128kB/8kB: H8S/2675
  • 64kB/8kB: H8S/2673
  • -/32kB: H8S/2674R
  • -/8kB: H8S/2670
• Ease of use:
  • EEPMOV instruction:Dummy read deleted
  • IPR independence (EXDMAC and IRQ)
  • A/D registers: 4 → 8 (more useful)
• Bus controller improved
  • OE signal added (for fast page/EDO)
  • 64Mb DRAM direct Interface supported
  • Two burst ROM areas (area 0/1)
• Various peripheral functions
  • 16 IRQs
  • EXDMAC x 4ch added
• Internal SDRAM interface: H8S/2678R Group
  • 64-Mbit direct connection interface
  • Hold times are assured by the dedicated SDRAM Φ
  • Includes a clock suspension function
• Package (QFP, LQFP)
  • FP-144G(20.0 x 20.0mm, 0.5mm pitch): H8S/2678 Group
  • FP-144H(20.0 x 20.0mm, 0.5mm pitch): H8S/2678R Group

Key Applications:

Car Audio, Game Music Instruments, Remote Controller, Office automation equipment, PC Peripherals (External memory, Input, Output), Communication equipment Telephone, home information appliances, Digital consumer applications, Printer MFP PPC LBP, and Photo printer Label Printer

Built-in Functions

• High-speed H8S/2000 central processing unit with 16-bit architecture
  • Upward-compatible with H8/300 and H8/300H CPUs on an object level
  • Sixteen 16-bit general registers
  • 69 basic instructions
  • Address space: 16M byte
• Interrupt
  • Internal: 56
  • External: 17
• Bus controller
  • External data bus width: 8/16 bits
• Varioius peripheral functions
  • DMA controller (DMAC)
  • EXDMA controller (EXDMAC)
  • Data transfer controller (DTC) x 85ch
  • 16-bit timer pulse unit (TPU) x 6ch
  • Programmable pulse generator (PPG) x 16ch
  • 8-bit timer (TMR) x 2ch
  • Watchdog timer (WDT) x 1ch
  • Asynchronous or clocked synchronous serial communication interface (SCI) x 3ch
  • 10-bit A/D converter x 12ch
  • 8-bit D/A converter x 4ch
  • Clock pulse generator
• General I/O ports
  • I/O pins: 103
  • Input-only pins: 12