The MPC8568E PowerQUICC™ III family is designed to address the increasing performance requirements for broadband access equipment including 3G/WiMAX/LTE basestations, RNC´s, gateways and ATM/TDM/IP equipment. The MPC8568E enables both IP and multi-protocol solutions, combining a high-performance e500 processor core built on Power Architecture™ technology scaling up to 1.33 GHz, a flexible communications engine and high-speed system interfaces, enabling customers to handle many functions in a single chip solution that otherwise would require multiple devices. Ultimately this high level of integration provides savings in cost, power and board space.

The MPC8568E provides multiprotocol support for both protocol termination and interworking for a wide range of communication protocols, including ATM, POS, Ethernet, PPP, HDLC and TDM - allowing the flexibility necessary for broadband access devices. Two enhanced Gigabit Ethernet ports, PCI Express® and Serial RapidIO® interconnect technology enables high-speed links to industrywide switches, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs) and digital signal processors (DSPs). An integrated security engine supports common encryption algorithms, including the Kasumi algorithm needed for 3G wireless security.

MPC8568E Family of Processors

The MPC8568E family consists of the MPC8568E and the MPC8567E. Both are offered in a 1023-pin FC-BGA package for pin compatibility.

Key Advantages

• High level of integration and performance, simplifying board design
• Consistent programming model across the PowerQUICC III family of processors
• Flexible system-on-chip (SoC) platform can help improve time to market
• 90 nm silicon-on-insulator (SOI) technology
• High-performance enhanced e500 core
  • 512 KB L2 cache
  • High internal processing bandwidth
• Integrated DDR/DDR2 memory controller
• Two integrated Triple Speed Ethernet Controllers (enhanced TSEC)
• Advanced QUICC Engine™ technology supports a wide range of protocols and associated interworking
• TLU provides off-load for table search functions associated with IP forwarding, firewall and Access Control List (ACL) applications
• Flexible high-speed interconnect interfaces:
  • Serial RapidIO interconnect technology
  • PCI Express support
• PCI and local bus interface support
• Integrated security engine

Features

• Embedded e500 core, scaling up to 1.33 GHz
  • 3199 MIPS at 1.33 GHz (estimated Dhrystone 2.1)
  • 36-bit physical addressing
  • Double-precision embedded floating-point
  • Memory management unit (MMU)
• Integrated L1/L2 cache
  • L1 cache - 32 KB data and 32 KB instruction
  • L2 cache - 512 KB (8-way set associative)
• Integrated DDR memory controller with full ECC support
• Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4
• Two on-chip, triple-speed Ethernet controllers supporting 10 Mbps, 100 Mbps and 1 Gbps Ethernet/IEEE® 802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces
• QUICC Engine technology
  • Protocol Support:
    • ATM SAR up to 622 Mbps (OC-12) full duplex
    • PPP, multilink (ML-PPP), multiclass (MC-PPP) and PPPmux
    • IP termination support for IPv4
    • L2 Ethernet interworking
    • ATM (AAL2/AAL5) to Ethernet (IP) interworking
    • Extensive support for Ethernet RMON/MIB statistics
    • 256 channels of HDLC/Transparent or 128 channels of SS#7
  • Serial Interfaces:
    • Two UL2/POS-PHY interfaces
    • Three 1 Gbps Ethernet interfaces using GMII. Two 1 Gbps Ethernet interfaces using RGMII, TBI and RTBI
    • Up to eight 10/100 Mbps Ethernet interfaces using MII or RMII
    • Up to eight T1/E1/J1 interfaces or two T3/E3 interfaces
    • Dual SPI interfaces
• Serial RapidIO and PCI Express high-speed interconnect interfaces
• Table lookup unit
• On-chip network (OCeaN) switch fabric
• 32-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
• 166 MHz, 32-bit, 3.3V I/O, local bus with memory controller
• Integrated four-channel DMA controller
• Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUART) support
• Programmable interrupt controller (PIC)
• IEEE 1149.1 JTAG test access port
• 1.1V core voltage with 3.3V, 2.5V and 1.8V I/O
• 1023-pin FC-BGA package