Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Memory
4352 bytes internal data RAM (256 + 4096)
64 kB (‘F93x) or 32 kB (‘F92x) Flash; In-system programmable in 1024-byte sectors—1024 bytes are reserved in the 64 kB devices
Digital Peripherals
24 or 16 port I/O; All 5 V tolerant with high sink current and programmable drive strength-Hardware SMBus™ (I2C™ Compatible), 2 x SPI™, and UART serial ports available concurrently
Four general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer
Hardware smaRTClock operates down to 0.9 V and requires less than 0.5 μA supply current.
Clock Sources
Internal oscillators: 24.5 MHz, 2% accuracy supports UART operation; 20 MHz low power oscillator requires very little bias current.
External oscillator: Crystal, RC, C, or CMOS Clock
smaRTClock oscillator: 32 kHz Crystal or internal
Can switch between clock sources on-the-fly; useful in implementing various power saving modes