CIP-51™ Microcontroller Core
Fully 8051 Compatible
The C8051Fxxx and C8051T6xx families of devices utilize Silicon Labs' proprietary CIP-51 microcontroller core. The CIP- 51 is fully compatible with the MCS-51™ instruction set and standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included with a standard 8052, including up to five 16-bit counter/timers, one or two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and up to 8 byte-wide I/O Ports.
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles and has a maximum system clock of 100 MHz. The CIP-51 has a total of 109 instructions