The DSP56800E architecture provides a variety of features that enhance performance, reduce application
cost, and ease product development. The architectural features that make these benefits possible include
the following:

• High Performance—The DSP56800E supports most mid-performance DSC applications.
  Compatibility—The DSP56800E is source-code compatible with the Freescale DSP56800 Family,
  making it a logical upgrade for performance-hungry applications. DSP56800 software can be run
  on the DSP56800E by simply recompiling or reassembling it.
• Ease of Programming—The DSP56800E’s instruction mnemonics are designed to resemble the
  mnemonics of MCUs, simplifying the transition from programming traditional microprocessors.
  Instruction-set support for both fractional and integer data types provides the flexibility that is
  necessary for optimal algorithm implementation.
• Support for High-Level Languages—The C programming language is well suited to the
  DSP56800E architecture. The majority of an application can be written in a high-level language
  without compromising DSC performance. A flexible instruction set and programming model enable
  the efficient generation of compiled code.
• Rich Instruction Set—In addition to supporting instructions that support DSC algorithms, the
  DSP56800E provides control, bit-manipulation, and integer processing instructions. Powerful
  addressing modes and a range of data sizes are also provided. The result is compact, efficient code.
• High Code Density—The base instruction word size for the DSP56800E is only 16 bits, with
  multi-word instructions for more complex operations, resulting in optimal code density. The
  instruction set emphasizes efficient control programming, which accounts for the largest portion of
  an application.
• Multi-Tasking Support—Implementing a real-time operating system or simple multi-tasking is
  much easier on the DSP56800E than on most DSCs. The architecture provides full support for a
  software stack, fast 32-bit context saves and restores to and from the system stack, atomic
  test-and-set operations, and four prioritized software interrupts.
• Precision—The DSP56800E core enables precise DSC calculations. Enough precision for 96 dB
  of dynamic range is provided by 16-bit data paths. Intermediate values in the 36-bit accumulators
  can range over 216 dB.
• Hardware Looping—Two types of zero-overhead hardware looping are provided, enhancing
  performance and making loop-unrolling techniques unnecessary.
  Parallelism—Each on-chip execution unit, memory device, and peripheral operates independently
  and in parallel. Because of the high level of parallelism, the following can be executed in a single
  instruction:
• Fetching the next instruction
• A 16-bit × 16-bit multiplication with 36-bit accumulation
• Optional negation, rounding, and saturation of the result
• Two 16-bit data moves
• No-overhead hardware looping
•  Two address pointer updates
• Invisible Instruction Pipeline—The eight-stage instruction pipeline provides enhanced
  performance while remaining essentially invisible to the programmer. Developers can program in
  high-level languages such as C without being concerned about the pipeline, even as they benefit
  from the pipeline’s throughput of one instruction per cycle.
• Low Power Consumption—Implemented in CMOS, the DSP56800E inherently consumes very
  little power. In addition, the core architecture supports two low-power modes, STOP and WAIT,
  which can provide even more power savings. The power management implementation can shut off
  unused sections of logic.
• Real-Time Debugging—Freescale’s Enhanced On-Chip Emulation technology (Enhanced
  OnCE™) allows simple, inexpensive, non-intrusive, and speed-independent access to the internal
  state of the DSP56800E core. By using Enhanced OnCE, programmers have full control over the
  processor’s operation, simplifying and speeding debugging tasks without having to halt the core.