The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

• Up to 667MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
  • Parity on Data and Tag address - checking of parity with error injection
  • Three logical regions in D-cache: Locked, Transient, and Normal
  • D-cache full-line flush capability
  • 41-bit virtual address, 36-bit (64GB) physical address
  • Superscalar, out-of-order execution
  • Seven-stage pipeline
  • Three execution pipelines
  • Dynamic branch prediction
  • Memory management unit
    • 64-entry, full associative, unified TLB with parity
    • Separate instruction and data micro-TLBs
    • Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
    • Debug facilities
      • Multiple instruction and data range breakpoints
      • Data value compare
      • Single step, branch, and trap events
      • Non-invasive real-time trace interface
      • 24 DSP instructions
        • Single cycle multiply and multiply-accumulate
        • 32 x 32 integer multiply