The next-generation ColdFire® microarchitecture provides a 2.8x performance improvement when compared
with the ColdFire 3 core over a broad range of applications.
Improved microarchitecture
for higher performance: greater than 200 Dhrystone 2.1 MIPS @ 150 MHz
Small set of new
instructions for better code density and performance
Enhanced MAC and debug functionality
Core size = 4.5 mm2 in 0.25 micron drawn process
Independent, decoupled pipelines
4-stage Instruction Fetch Pipeline (IFP)
5-stage Operand Execution Pipeline
FIFO
I-Buffer is the decoupling mechanism
Limited superscalar execution through use of
instruction folding
Approaches dual-issue performance but at a much lower silicon
cost
Harvard memory architecture
Most instructions execute in 1 cycle
Sophisticated 2-level branch acceleration mechanisms in the IFP minimize execution time of
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