740
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CENTRAL PROCESSING UNIT (CPU)
Six main registers are built into the CPU of the 740 Family.
The Program Counter (PC) is a sixteen-bit register; however, the Accumulator (A), Index Register X (X), Index Register Y (Y), Stack Pointer (S) and Processor Status Register (PS) are eight-bit registers.
Note: Except for the I flag, the contents of these registers are indeterminate after a hardware reset; therefore, initialization is required with some programs (immediately after reset the I flag is set to “1”).
Accumulator (A)
The Accumulator, an eight-bit register, is the main register of the microcomputer. This general-purpose register is used most frequently for arithmetic operations, data transfer, temporary memory, conditional judgments, etc.
Index Register X (X), Index Register Y (Y)
The 740 Family has an Index Register X and an Index Register Y, both of which are eight bit registers.
When using addressing modes which use these index registers, the address, which is added the contents of Index Register to the address specified with operand, is accessed. These modes are extremely effective for referencing subroutine and memory tables. The index registers also have increment, decrement, compare, and data transfer functions; therefore, these registers can be used as simple accumulators.
Stack Pointer (S)
The Stack Pointer is an eight-bit register used for generating interrupts and calling subroutines. When an interrupt is received, the following procedure is performed automatically in the
indicated sequence:
(1) The contents of the high-order eight bits of the Program Counter (PCH) are saved to an address using the Stack Pointer contents for the low-order eight bits of the address.
(2) The Stack Pointer contents are decremented by 1.
(3) The contents of the low-order eight bits of the Program Counter (PCL) are saved to an address using the Stack Pointer Contents for the low-order eight bits of the address.
(4) The Stack Pointer contents are decremented by 1.
(5) The contents of the Processor Status Register (PS) are saved to an address using the Stack Pointer contents for the low-order eight bits of the address.
(6) The Stack Pointer contents are decremented by 1.
The Processor Status Register is not saved when calling subroutines (items (5) and (6) above are not executed). The Processor Status Register is saved by executing the PHP instruction in software.
To prevent data loss when generating interrupts and calling subroutines, it is necessary to save other registers as well. This is done by executing the proper instruction in software while in the interrupt service routine or subroutine.
The high-order eight bits of the address are determined by the Stack Page Selection Bit. For example, the PHA instruction is executed to save the contents of the Accumulator.
Executing the PHA instruction saves the Accumulator contents to an address using the Stack Pointer contents as the low-order eight bits of the address.
The RTI instruction is executed to return from an interrupt routine. When the RTI instruction is executed, the following procedure is performed automatically in sequence.
(1) The Stack Pointer contents are incremented by 1.
(2) The contents of an address using the Stack Pointer contents as the low-order eight bits of the address is returned to the Processor Status Register (PS).
(3) The Stack Pointer contents are incremented by 1.
(4) The contents of an address using the Stack Pointer as the low-order eight bits of the address is returned to the low-order eight bits of the Program Counter (PCL).
(5) The Stack Pointer contents are incremented by 1.
(6) The contents of an address using the Stack Pointer as the low-order eight bits of the address is returned to the high-order eight bits of the Program Counter (PCH).
Steps (1) and (2) are not performed when returning from a subroutine using the RTS instruction. The Processor Status Register should be restored before returning from a subroutine by using the PLP instruction. The Accumulator should be restored before returning from a subroutine or an interrupt servicing routine by using the PLA instruction.
The PLA and PLP instructions increment the Stack Pointer by 1 and return the contents of an address stored in the Stack Pointer to the Accumulator or Processor Status Register, respectively.
Program Counter (PC)
The Program Counter is a sixteen-bit counter consisting of PCH and PCL, which are each eight-bit registers. The contetnts of the Program Counter indicates the address which an instruction to be executed next is stored.
The 740 Family uses a stored program system; to start a new operation it is necessary to transfer the instruction and relevant data from memory to the CPU. Normally the Program Counter is used to indicate the next memory address. After each instruction is executed, the next instruction required is read. This cycle is repeated until the program is finished.
Note: The control of the Program Counter of the 740 Family is almost fully automatic. However, caution must be exercised to avoid differences between program flow and Program Counter contents when using the Stack Pointer or directly altering the contents of the Program Counter.
Processor Status Register (PS)
The Processor Status Register is an eight-bit register consisting of 5 flags which indicate the status of arithmetic operations and 3 flags which determine operation. Immediately after a reset, only the interrupt disable flag is set to “1,” and the other flags are undefined. Therefore, initialize the flags that effect program execution. Especially, initialize the T and D flags because of their effect on operation.
Each of these flags is described below. Table 2.5.1 lists the instructions to set/clear each flag. Refer to the section “Appendix 2 MACHINE LANGUAGE INSTRUCTION TABLE” or “3.3 INSTRUCTIONS” for details on when these flags are altered.
[ Carry flag C ]------------------------------------------------------ Bit 0
This flag stores any carry or borrow from the Arithmetic Logic Unit (ALU) after an arithmetic operation and is also changed by the Shift or Rotate instruction.
This flag is set by the SEC instruction and is cleared by the CLC instruction.
[ Zero flag Z ] ------------------------------------------------------- Bit 1
This flag is set when the result of an arithmetic operation or data transfer is “0” and is
cleared by any other result.
[ Interrupt disable flag I ] ---------------------------------------- Bit 2
This flag disables interrupts when it is set to “1.” This flag immediately becomes “1” when
an interrupt is received.
This flag is set by the SEI instruction and is cleared by the CLI instruction.
[ Decimal mode flag D ] ----------------------------------------- Bit 3
This flag determines whether addition and subtraction are performed in binary or decimal
notation. Addition and subtraction are performed in binary notation when this flag is set to
“0” and as a 2-digit, 1-word decimal numeral when set to “1.” Decimal notation correction
is performed automatically at this time.
This flag is set by the SED instruction and is cleared by the CLD instruction.
Only the ADC and SBC instructions are used for decimal arithmetic operations.
Note that the flags N, V and Z are invalid when decimal arithmetic operations are performed
by these instructions.
[ Break flag B ] ----------------------------------------------------- Bit 4
This flag determines whether an interrupt was generated with the BRK instruction. When a
BRK instruction interrupt occurs, the flag B is set to “1” and saved to the stack; for all other
interrupts the flag is set to “0” and saved to the stack.
[ X modified operation mode flag T ] ----------------------- Bit 5
This flag determines whether arithmetic operations are performed via the Accumulator or
directly on a memory location. When the flag is set to “0”, arithmetic operations are
performed between the Accumulator and memory. When “1”, arithmetic operations are
performed directly on a memory location.
This flag is set by the SET instruction and is cleared by the CLT instruction.
(1) When the T flag = 0
A ← A * M2
* : indicates an arithmetic operation
A: accumulator contents
M2: contents of a memory location specified by the addressing mode of the
arithmetic operation
(2) When the T flag = 1
M1 ← M1 * M2
* : indicates arithmetic operation
M1: contents of a memory location, designated by the contents of Index
Register X.
M2: contents of a memory location specified by the addressing mode of
arithmetic operation.
[ Overflow flag V ] ------------------------------------------------- Bit 6
This flag is set to “1” when an overflow occurs as a result of a signed arithmetic operation.
An overflow occurs when the result of an addition or subtraction exceeds +127 (7F16) or
–128 (8016) respectively.
The CLV instruction clears the Overflow Flag. There is no set instruction.
The overflow flag is also set during the BIT instruction when bit 6 of the value being tested
is “1.”
Note: Overflows do not occur when the result of an addition or subtraction is equal to or smaller than the above numerical values, or for additions involving values with different signs.
[ Negative flag N ] ------------------------------------------------- Bit 7
This flag is set to match the sign bit (bit 7) of the result of a data or arithmetic operation. This flag can be used to determine whether the results of arithmetic operations are positive or negative, and also to perform a simple bit test.
Addressing Modes
The 740 Family has 19 addressing modes and a powerful memory access capability. When
extracting data required for arithmetic and logic operations from memory or when storing the
results of such operations in memory, a memory address must be specified. The specification
of the memory address is called addressing. The 740 Family instructions can be classified into three kinds, by the number of bytes required in program memory for the instruction: 1-byte, 2-byte and 3-byte instructions. In each case, the first byte is known as the “Op-Code (operation code)” which forms the basis of the instruction. The second or third byte is called the “operand” which affects the addressing. The contents of index registers X and Y can also effect the addressing.
Although there are many addressing modes, there is always a particular memory location specified. What differs is whether the operand, or the index register contents, or a combination
of both should be used to specify the memory or jump destination. Based on these 3 types
of instructions, the range of variation is increased and operation is enhanced by combinations
of the bit operation instructions, jump instruction, and arithmetic instructions.
As for 1-byte instruction, an accumulator or a register is specified, so that the instruction does
not have “operand,” which specify memory. |
