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Home » XC800 » XC800 I-Series
XC800 I-Series Processors 
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XC800 I-Series
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The Infineon XC800 microcontroller family has a CPU which is functionally upward compatible to the 8051. While the standard 8051 CPU is designed around a 12-clock machine cycle, the XC800 CPU uses a two-clock period machine cycle.
The instruction set consists of 45% one-byte, 41% two-byte, and 14% three-byte instructions. Each instruction takes 1, 2 or 4 machine cycles to execute. In case of access to slower memory, the access time may be extended by wait states.
The XC800 microcontrollers support via the dedicated JTAG interface or the standard UART interface, a range of debugging features including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and special function registers.
The key features of the XC800 microcontrollers are listed below.
•Two clocks per machine cycle
•Up to 1 Mbyte of external data memory; up to 256 bytes of internal data memory
•Up to 1 Mbyte of program memory
•Support for synchronous or asynchronous program and data memory
•Wait state support for slow memory
•Program memory download option
•15-source, 4-level interrupt controller
•Up to eight data pointers
•Power saving modes
•Dedicated debug mode via the standard JTAG interface or UART
•Two 16-bit timers (Timer 0 and Timer 1)
•Full-duplex serial port (UART) |
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