F28x Floating-point Series
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The F28x Floating-point Series devices contain both the TMS320C28x DSP CPU and the TMS320C28x Floating Point Unit.
TMS320C28x DSP CPU Overview:
The TMS320C28x™ is one of several fixed-point CPUs in the TMS320™ family.The C28x™ is source-code and object-code compatible with the C27x™. In addition, much of the code written for the C2xLP CPU can be reassembled to run on a C28x™ device. The C2xLP CPU is used in all TMS320F24xx and TMS320C20x devices and their derivatives. This refers to C2xLP as a generic name for the CPU used in these devices.
The CPU is a low-cost 32-bit fixed-point processor. This device draws from thebest features of digital signal processing; reduced instruction set computing(RISC); and microcontroller architectures, firmware, and tool sets. The CPUfeatures include a modified Harvard architecture and circular addressing. TheRISC features are single-cycle instruction execution, register-to-register operations,and modified Harvard architecture (usable in Von Neumann mode).
The microcontroller features include ease of use through an intuitive instructionset, byte packing and unpacking, and bit manipulation.The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and datawhile it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
TMS320C28x Floating Point Unit Overview:
The TMS320C2000™ DSP family consists of fixed-point and floating-point digital signal controllers (DSCs). TMS320C2000™ Digital Signal Controllers combine control peripheral integration and ease of use of a microcontroller (MCU) with the processing power and C efficiency of TI’s leading DSP technology.
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by adding registers and instructions to support IEEE single-precision floating point operations. This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The DSC features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture (usable in Von Neumann mode). The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
The C28x+FPU contains:
· A central processing unit for generating data and program-memory addresses; decoding and executing instructions; performing arithmetic, logical, and shift operations; and controlling data transfers among CPU registers, data memory, and program memory
· A floating-point unit for IEEE single-precision floating point operations.
· Emulation logic for monitoring and controlling various parts and functions of the device and for testing device operation. This logic is identical to that on the C28x fixed-point CPU.
· Signals for interfacing with memory and peripherals, clocking and controlling the CPU and the
emulation logic, showing the status of the CPU and the emulation logic, and using interrupts. This logic is identical to the C28x fixed-point CPU.
Some features of the C28x+FPU central processing unit are:
· Fixed-Point instructions are pipeline protected. This pipeline for fixed-point instructions is identical to that on the C28x fixed-point CPU. The CPU implements an 8-phase pipeline that prevents a write to and a read from the same location from occurring out of order.
· Some floating-point instructions require pipeline alignment. This alignment is done through software to allow the user to improve performance by taking advantage of required delay slots.
· Independent register space. These registers function as system-control registers, math registers, and data pointers. The system-control registers are accessed by special instructions.
· Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arithmetic and Boolean logic operations.
· Floating point unit (FPU). The 32-bit FPU performs IEEE single-precision floating-point operations.
· Address register arithmetic unit (ARAU). The ARAU generates data memory addresses and
increments or decrements pointers in parallel with ALU operations.
· Barrel shifter. This shifter performs all left and right shifts of fixed-point data. It can shift data to the left by up to 16 bits and to the right by up to 16 bits.
· Fixed-Point Multiplier. The multiplier performs 32-bit ´ 32-bit 2s-complement multiplication with a 64-bit result. The multiplication can be performed with two signed numbers, two unsigned numbers, or one signed number and one unsigned number. |
