The ARM Cortex-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest performance, most power-efficient processor ever developed by ARM. With the ability to scale in speed from 600MHz to greater than 1GHz, the Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing operation in less than 300mW; and performance-optimized consumer applications requiring 2000 Dhrystone MIPS. The Cortex-A8 processor is ARM’s first superscalar processor featuring technology for enhanced code density and performance, NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target) technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages.

The exceptional speed and power efficiency of the Cortex-A8 processor is enabled by new ARM Artisan® Advantage-CE libraries supporting and implementing advanced leakage control.

The processor is supported by a wide range of ARM technologies for rapid system design including:

• RealView® DEVELOP family of software development tools
• RealView CREATE family of ESL tools and models
• CoreSight™ debug and trace technology; and software library support through the OpenMAX multimedia processing standard.
• AMBA® 3 AXI high-performance SoC interconnect

• In-order, dual-issue, superscalar microprocessor core
  • 13-stage main integer pipeline
  • 10-stage NEON media pipeline
  • Dedicated L2 cache with programable wait states
  • Global history based branch prediction
• Works in conjunction with a power optimized load store pipeline to deliver 2.0 DMIPS/MHz for power sensitive applications
• ARMv7 Architecture compliant including
  • Thumb-2 technology for greater performance, energy efficiency, and code density
  • NEON™ signal processing extensions to accelerate media codecs such as H.264 and MP3
  • Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and reduce memory footprint by up to three times
  • TrustZone technology for secure transactions and Digital Rights Management (DRM)
• Integrated Level 2 Cache
  • Built using standard compiled RAMs
  • configurable size from 64K – 2MB
  • Programmable delay
• Optimized Level 1 Caches
  • Performance and power optimized
  • Combine minimal access latency with hash way determination to maximize performance and minimize power consumption.
• Dynamic Branch Prediction
  • Enabled by branch target and global history buffers
  • Achieves 95% accuracy across industry benchmarks.
  • Replay mechanism minimizes miss-predict penalty
• Memory System
  • Single-cycle load-use penalty for access to the L1 cache
  • Hash array in the L1 cache limits activation of the memories to when they are likely to be needed.
  • Direct interface between the integrated, configurable L2 cache and the NEON media unit for data streaming
  • Banked L2 cache design that enables only one bank at a time
  • Support for multiple outstanding transactions to the L3 memory to fully utilize the CPU