Tensilica provides SOC designers with everything needed to quickly design small, low power and high-speed dataplane processors that exactly match the required application. By using Tensilica’s Xtensa dataplane processing units (DPUs), design teams can significantly reduce the development and verification time required by hand-coding RTL blocks in Verilog or VHDL. As these DPUs provide programability into the dataplane, changes can be made in firmware after silicon production that extend the life of the product as standards develop and market needs change.
All Xtensa customizable processors have two essential features:
Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need - including multiple pre-verified DSP engines
Extensibility - designers can add their own instructions, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology. The designer only has to specify the functional behavior of the new data path elements in the TIE language (Verilog-like) and then the RTL and whole tool chain is automatically generated.
Complete with Matching SW Tool Chain
All of the tools, including the compiler, debugger and ISS, are automatically updated to match the configuration options and any custom extensions. The matching tool set is generated by the Xtensa Processor Generator at the same time the new processor RTL is created.
