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Renesas 78K0R


  • Minimum instruction execution time can be changed from high speed (0.05 μs: @ 20 MHz operation with highspeed system clock) to ultra low-speed (61 μs: @ 32.768 kHz operation with subsystem clock)
  • General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
  • ROM, RAM capacities
  • On-chip multiplier/divider (16 bits × 16 bits, 32 bits ÷ 32 bits