The design goals we established for the MCUs in the RX family were very aggressive, to say the least. Using existing Renesas MCUs as a reference, our basic R&D objectives included
Five times the maximum operating frequency
Twice the processing performance (in terms of MIPS/MHz),
A 30% increase in code efficiency
A 2/3 cut in power consumption
Quantitative goals included
A maximum operating frequency of 200MHz
Processing performance of 1.65MIPS/MHz
A CPU current of 0.03mA/MHz
More flash memory capacity: up to 4MB.
These design goals have been met. To achieve these improved levels of performance and capability, a different approach to the architecture was required. Neither a conventional RISC nor a conventional CISC approach would suffice.
The innovative Renesas solution was to combine the advantages of the high-speed RISC CPU designs refined in our SuperH family with those of the flexible, code-efficient CISC designs nurtured in our H8S/H8SX and the M16C/R32C families. Specifically, to create a next-generation CPU architecture, the RX design team added the general-purpose register machine Harvard architecture and 5-stage pipeline of RISC to the byte variable-length instructions of CISC . This clever design approach was made possible by building on decades of MCU design experience and applying a large library of accumulated IP.
The process of developing the RX architecture obviously involved many steps. A very important one was to find the best combination of elements of RISC and CISC CPUs. To do that, the design team conducted benchmark tests using application software for each of the key target markets for the devices, especially the office automation, consumer, industrial, and automotive fields. After analyzing the test data, the engineers identified the optimal solution for performance and code efficiency, and then applied the appropriate architectural elements to the RX CPU.
A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory.
The CPU has 73 basic instructions and 8 floating-point operation instructions, and 9 DSP instructions, for a total of 90 instructions. It has 10 addressing modes and caters to register–register operations, register–memory operations, immediate–register operations, immediate–memory operations, memory–memory transfer, and bitwise operations. High-speed operation was realized by achieving execution in a single cycle not only for register–register operations, but also for other types of multiple instructions. The CPU includes an internal multiplier and an internal divider for high-speed multiplication and division.
The RX CPU has a five-stage pipeline for processing instructions. The stages are instruction fetching, instruction decoding, execution, memory access, and write-back. In cases where pipeline processing is drawn-out by memory access, subsequent operations may in fact be executed earlier. By adopting "out-of-order completion" of this kind, the execution of instructions is controlled to optimize numbers of clock cycles.