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XC800

Introduction:

The Infineon XC800 microcontroller family has a CPU which is functionally upward compatible to the 8051. While the standard 8051 CPU is designed around a 12-clock machine cycle, the XC800 CPU uses a two-clock period machine cycle.
The instruction set consists of 45% one-byte, 41% two-byte, and 14% three-byte instructions. Each instruction takes 1, 2 or 4 machine cycles to execute. In case of access to slower memory, the access time may be extended by wait states.

Memory Organization:

The memory partitioning of the XC800 microcontrollers is typical of the Harvard architecture where data and program areas are held in separate memory space. The on-chip peripheral units are accessed using an internal Special Function Register (SFR) memory area that occupies 128 bytes of address, which can be mapped or paged to increase the number of addressable SFRs.
A typical memory map of the code space consists of internal ROM/Flash, on-chip Boot ROM, an on-chip XRAM and/or external memory. The memory map of the data space is typical of the standard 8051 architecture: the internal data memory consists of 128 bytes of directly addressable Internal RAM (IRAM) and 128 bytes of indirect addressable IRAM. On-chip ‘external’ RAM (XRAM) is also supported. External data memory may be supported outside of the internal range.

CPU Architecture:

The CPU consists mainly of the instruction decoder, the arithmetic section, the program control section, the access control section, and the interrupt controller. The CPU also supports power saving modes.
The instruction decoder decodes each instruction and accordingly generates the internal signals required to control the functions of the individual units within the CPU. These internal signals have an effect on the source and destination of data transfers and control the ALU processing.
The arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic/logic unit (ALU), A register, B register, and PSW register. The ALU accepts 8-bit data words from one or two sources, and generates an 8-bit result under the control of the instruction decoder. The ALU performs both arithmetic and logic operations. Arithmetic operations include add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust, and compare. Logic operations include AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). A Boolean unit is also included for performing the bit operations such as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear, and move to/from carry. The ALU can perform the bit operations of logical AND or logical OR between any addressable bit (or its complement) and the carry flag, and place the new result in the carry flag.
The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.
The access control unit is responsible for the selection of the on-chip memory resources. The interrupt requests from the peripheral units are handled by the interrupt controller unit.