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TriCore®

TriCore® is the first single-core 32-bit MCU-DSP architecture optimized for real-time embedded systems that truly unifies the best of three worlds - real-time capabilities of microcontrollers, computational power of DSPs, and the price/performance benefits of RISC load-store architectures. It includes the TriCore® 1 and TriCore® 2 Core Variants
TriCore® 1 is the first single-core 32-bit microcontroller-DSP architecture optimized for real-time embedded systems. TriCore® unifies the best of 3 worlds - real-time capabilities of  microcontrollers, computational prowess of DSPs, and highest performance/price implementations of RISC loadstore architectures.
TriCore® 2 is primarily a micro architecture redesign of the TriCore® 1 architecture, and is essentially backwards compatible. However there are several upgrades to the TriCore® 2 architecture, as follows: Improved Operating System and Management Instructions, Enhanced Memory Model, Enhanced On-Chip Debug Support (OCDS), Multi-Threading Mechanism, New Instructions, Flexible Indexed Addressing Mode, Updated Trap Model.

MCU Features
• Fast context switch & low interrupt latency
• 16-bit and 32-bit instruction formats
• Powerful bit manipulation support
DSP Features
• Sustained throughput of two 16x16 MACs per clock
• SIMD packed arithmetic and zero overhead loops
• DSP addressing modes and saturated math
Processor Features
• 32-bit load-store Harvard architecture
• Superscalar execution
• 16 address and 16 data registers
TriCore Benefits
• Integrated MCU-DSP instructions in one core
• Fast and efficient processing of multiple tasks on one engine
• Low code size and inherent high level language support
• One development toolset for both MCU and DSP tasks
• Higher flexibility and lower cost

TriCore Units & Interfaces

Superscalar Four-Stage Pipelined CPU
• 32-bit Load/Store Harvard Architecture
• 3 pipelines: Arithmetic, Load-Store, & Loop
• Single instruction Multiple Data capability Control Features
• Single-bit addressing and manipulation
• Extract and insert data field instructions
• Fast context switching (from 4 cycles)
• 16 & 32-bit instructions, intermixable without boundary penalty

DSP Features
• Dual 16-bit Multiplier Accumulators
• Zero overhead loops
• Addressing: Circular, bit-reverse, register indirect with post & pre-increment
• Rounding, truncation, saturation, signed fraction support Memory Protection
• Native protection scheme
• Optional MMU Coprocessor Interface
• Up to 3 coprocessor available
• Floating Point coprocessor available Program Memory Interface (PMI)
• 64-bit interface for up to 64KB of configurable, tightly coupled cache/scratchpad memory Data Memory Interface (DMI)
• 128-bit interface for up to 64KB of configurable, tightly coupled cache/scratchpad memory Local Memory Bus (LMB)
• 64-bit data, 32-bit address
• Runs at CPU clock speed and supports 8, 16, 32 and 64-bit transfers
• Support for dual external interfaces Flexible Peripheral Interface (FPI) Bus
• 32-bit address and data de-multiplexed
• Single and multiple transfers: 8, 16 and 32-bit Interrupt Controller
• Programmable: Up to 255 Interrupt priorities/sources Debug Interface for Advanced Emulation
• Access to internal registers and memory through JTAG port
• Hardware, software and external breakpoints
• Support for trace functionality