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Freescale 56800DSC

The DSP56800 core is a programmable CMOS 16-bit DSP designed for efficient real-time digital signal processing and general purpose computing. The DSP56800 core is composed of four functional units that operate in parallel to increase throughput of the machine. The functional blocks-the program controller, Address Generation Unit (AGU), Data Arithmetic Logic Unit (Data ALU), and bit manipulation unit-each contain their own register set and control logic so that they may operate independently and in parallel with the other three. Each functional unit interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal address and data buses. Thus, it is possible for the Program Controller to be fetching a first instruction, the Address Generation Unit to generate up to two addresses for a second instruction, and the Data ALU to perform a multiply in a third instruction. Alternatively, it is possible for the bit manipulation unit to perform an operation in the third instruction described above in place of an operation in the Data ALU. The architecture is pipelined to take advantage of the parallel units and significantly decrease the execution time of each instruction.The major components of the DSP56800 core are the following:

  • Data ALU
  • Address Generation Unit (AGU)
  • Program controller and hardware looping unit
  • Bit manipulation unit
  • Three internal address buses
  • Four internal data buses
  • OnCE debug port
  • Clock generation circuitry

The architecture of the DSP56800 core has been streamlined and tuned for efficient DSP processing, compact DSP and controller code size, and excellent compiler performance. Several of the high performance signal processing features are described the next section.

Features of the DSP core.

  • 30 Million Instructions Per Second (MIPS) with a 60 MHz clock at 4.57 V-5.5 V
  • 20 Million Instructions Per Second (MIPS) with a 40 MHz clock at 2.7 V-3.6V
  • Parallel instruction set with useful DSP addressing modes
  • Single-cycle 16 ´ 16-bit parallel Multiplier-Accumulator (MAC)
  • 2 x 36-bit accumulators, including extension bits
  • Single-cycle 16-bit barrel shifter
  • Hardware DO and REP loops
  • Three 16-bit internal core data buses and three 16-bit internal address buses
  • One 16-bit Peripheral Interface Data Bus
  • Instruction set supports both DSP and controller functions
  • Controller style addressing modes and instructions for smaller code size
  • Efficient ‘C’ Compiler and local variable support
  • Hooks on core for 1 Mbyte program address space
  • Software subroutine and interrupt stack with unlimited depth