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Microchip PIC®

RISC-based Architecture

The PIC microcontroller architecture is based on a modified Harvard RISC instruction set that provides an easy migration path from 6 to 80 pins and from 384 bytes to 128K bytes of program memory. By combining the RISC features with a modified Harvard dual-bus architecture, Microchip's fast and flexible 10 MIPS PIC18F core is the most popular architecture for new microcontroller designs. A simple instruction set and seamless migration between product families makes PIC microcontrollers the logical choice for designs requiring flexibility and performance.

  • 12-, 14- and 16-bit wide instructions are upward compatible and tailored to maximize processing efficiency and boost performance
  • Instructions and data are transferred on separate buses, avoiding processing bottlenecks and increasing overall system performance
  • Two-stage pipelining enables one instruction to be executed while the next instruction is fetched
  • Single wide-word instructions increase software code efficiency and reduce required program memory