Language: English | Deutsch | 中国的       Change Country
NSC COP8

The COP8 uses separate instruction and data spaces (Harvard architecture). Instruction address space is 15 bits (32 KiB maximum), while data addresses are 8 bits (256 bytes maximum, extended via bank-switching). To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address. The CPU has an 8-bit accumulator and 15-bit PC. 16 additional 8-bit registers (R0–R15) and an 8-bit program status word are memory mapped. There are special instructions to access them, but general RAM access instructions may also be used.